The present invention concerns data communications between electronic devices or circuits, particularly programmable phase-lock loops suitable for use in high-speed receivers, transmitters, and transceivers.
In the computer and telecommunications industries, many electronic devices are typically coupled together to operate as systems. For example, computers are often connected to printers, scanners, cameras, and even other computers. In such systems, a common occurrence is the communication of data between two devices, a sending device and a receiving device.
The sending device generally has the data in the initial form of a set of digital words (sets of ones and zeros). A circuit, known as a transmitter in the sending device, converts each word into a string or sequence of electrical pulses, with each pulse timed according to a data clock, and transmits the timed sequence of pulses through a cable or other connector to the receiving device. The receiving device includes a receiver circuit that first determines the timing of the pulses and then identifies each of the pulses in the signal as a one or zero, enabling it to reconstruct the original digital words.
A key component in both the transmitter and the receiver is the phase-lock loop. The phase-lock loop is a circuit that generates a high-speed clock for transmitting data in the transmitter, and that measures the timing of the pulses in a received data signal. In particular, the phase-lock loop compares the received data signal to an internally produced oscillating signal, and continuously adjusts the frequency of the oscillating signal to match or lock on that of the received data signal.
One problem with phase-lock loops and thus the transmitter and receiver circuits that incorporate them is that they are generally tuned, or tailored, to operate with data signals of a certain frequency. This means that one cannot generally use a transmitter or receiver circuit having a phase-lock loop tuned for data signals of one frequency with data signals of another signal. The inability to communicate at other frequencies limits the usefulness of the transmitter and receiver circuits and their electronic devices.
One approach to allow for an adjustable phase-lock loop is reported in John G. Maneatis, Low-Jitter Process Independent DLL and PLL based on Self-Biased Techniques, IEEE Journal of Solid-State Circuits, Vol. 31, No. 11(1996). However, the reported circuit appears to be vulnerable to stability problems at gigabit frequencies, which may prevent it from properly locking onto some input signals. Additionally, the circuit includes active resistor components, which the present inventors believe will be difficult to implement with low-voltage power supplies.
Accordingly, there is a need for better programmable phase-lock loops.
To address these and other needs, the present inventors devised a digitally programmable phase-locked loop which operate at a frequency selected from a set of two or more frequencies.
An exemplary embodiment of the programmable phase-lock loop includes a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider. The charge pump, loop filter, and oscillator are all responsive to a programmable input which selects the frequency of the phase-lock loop. Notably, the programmability of these three components enables the exemplary embodiment to maintain a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting stability and rapid settling at each frequency setting.
Other aspects of the invention include a receiver, transmitter, and transceiver that incorporate a digitally programmable phase-lock loop. One exemplary receiver includes a phase-lock loop with four programmable components: a charge pump, a loop filter, a controlled oscillator, and a transconductor.